Clock recovery techniques (CRT) useful in a wide variety of communication systems based on wireless, optical and wireline links, include: a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality, a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing clocks, waveforms or messages, receiver synchronization techniques (RST) contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock.