Invention Grant
- Patent Title: FIFO buffer system providing same clock cycle response to pop commands
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Application No.: US13459841Application Date: 2012-04-30
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Publication No.: US09641464B2Publication Date: 2017-05-02
- Inventor: Robert T. Greenwood , Robert Bahary
- Applicant: Robert T. Greenwood , Robert Bahary
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: G06F12/00
- IPC: G06F12/00 ; H04L12/861

Abstract:
A first-in first-out (FIFO) buffer system includes FIFO control logic and first and second storage partitions. Each storage partition includes a corresponding single-port memory bank and a prefetch buffer. The FIFO control logic alternates processing of PUSH commands between the first and second storage partitions. Additionally, the FIFO control logic anticipates POP commands based on the FIFO order and the alternating PUSH arrangement by initiating prefetches of data so that data to be accessed by a POP command is available at either the prefetch buffer (if the prefetch has completed) or the output of the single-port memory bank (if the prefetch has not yet completed) of the corresponding storage partition at the time the POP command is received, thereby enabling the output of the data for the POP command in the same clock cycle in which the POP command is received.
Public/Granted literature
- US20130290646A1 FIFO BUFFER SYSTEM PROVIDING SAME CLOCK CYCLE RESPONSE TO POP COMMANDS Public/Granted day:2013-10-31
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