Invention Grant
- Patent Title: Adaptive cache memory controller
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Application No.: US14313055Application Date: 2014-06-24
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Publication No.: US09645920B2Publication Date: 2017-05-09
- Inventor: Abhijeet P. Gole , Ram Kishore Johri
- Applicant: Marvell World Trade LTD.
- Applicant Address: BB St. Michael
- Assignee: Marvell World Trade LTD.
- Current Assignee: Marvell World Trade LTD.
- Current Assignee Address: BB St. Michael
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/02 ; G06F12/0802 ; G06F12/0871

Abstract:
A system comprises a partitioning module and a writing module. The partitioning module is configured to partition each of a plurality of solid-state disks into a plurality of blocks. Each of the plurality of blocks has a predetermined size. The writing module is configured to write data to one or more of the plurality of solid-state disks in a sequence starting from a first block of a first solid-state disk of the plurality of solid-state disks to a first block of a last solid-state disk of the plurality of solid-state disks, and subsequently starting from a second block of the first solid-state disk to a second block of the last solid-state disk. In each of each of the plurality of the plurality of solid-state disks, the second block is subsequent to the first block.
Public/Granted literature
- US20140379965A1 ADAPTIVE CACHE MEMORY CONTROLLER Public/Granted day:2014-12-25
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