In at least some embodiments, a processor core generates one or more store operations by executing one or more store instructions in an instruction sequence. The one or more store operations are marked as a high priority store operations in response to detecting, in the instruction sequence, a window opening instruction and a window closing instruction bounding the one or more store instructions and are not so marked otherwise. The one or more store operations are buffered in a store queue associated with a cache memory of the processor core. Handling of the one or more store operations in the store queue is expedited in response to the one or more store operations being marked as high priority store operations and not expedited otherwise.