Invention Grant
- Patent Title: Modeling transistor performance considering non-uniform local layout effects
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Application No.: US14748643Application Date: 2015-06-24
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Publication No.: US09646124B2Publication Date: 2017-05-09
- Inventor: Dureseti Chidambarrao , Richard Q. Williams
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb & Riley, LLC
- Agent Jennifer M. Anda
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50

Abstract:
In a system and method, a design layout defines a transistor, a local layout effect (LLE)-inducing feature and shapes, including a non-uniform shape, that illustrate separation between the channel region and LLE-inducing feature. Layout information for the non-uniform shape, including minimum and maximum distances between the channel region and LLE-inducing feature, is extracted. Based on this layout information, a first width of a first portion of the non-uniform shape, which is associated with the maximum distance, and a second width of a second portion of the non-uniform shape, which is associated with the minimum distance, are derived and used to calculate the non-uniform shape's contribution to the value of a model parameter adjuster. The value of the model parameter adjuster is then calculated based on a sum of contributions from all shapes and used to generate a compact model for modeling a performance attribute of the transistor within the IC.
Public/Granted literature
- US20160378888A1 MODELING TRANSISTOR PERFORMANCE CONSIDERING NON-UNIFORM LOCAL LAYOUT EFFECTS Public/Granted day:2016-12-29
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