Invention Grant
- Patent Title: Monolithic three dimensional memory arrays with staggered vertical bit lines and dual-gate bit line select transistors
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Application No.: US14522777Application Date: 2014-10-24
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Publication No.: US09646691B2Publication Date: 2017-05-09
- Inventor: Chang Siau
- Applicant: SanDisk 3D LLC
- Applicant Address: US TX Plano
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Plano
- Agency: Vierra Magen Marcus LLP
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/34 ; G11C13/00 ; H01L45/00 ; H01L27/24

Abstract:
A monolithic three-dimensional memory array is provided that includes global bit lines disposed above a substrate, each global bit line having a long axis, vertically-oriented bit lines disposed above the global bit lines, word lines disposed above the global bit lines, memory cells coupled between the vertically-oriented bit lines and the word lines, and vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines. Each vertically-oriented bit line select transistor has a width, a first control terminal and a second control terminal. The word lines and the vertically-oriented bit lines have a half-pitch, and the width of the vertically-oriented bit line select transistors is between about two times the half-pitch and about three times the half-pitch. Vertical bit lines disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines.
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