Invention Grant
- Patent Title: Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models
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Application No.: US15081740Application Date: 2016-03-25
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Publication No.: US09651619B2Publication Date: 2017-05-16
- Inventor: Adnan Hamid , Kairong Qian , Kieu Do , Joerg Grosse
- Applicant: Breker Verification Systems
- Applicant Address: US CA San Jose
- Assignee: Breker Verification Systems
- Current Assignee: Breker Verification Systems
- Current Assignee Address: US CA San Jose
- Agency: Martine Penilla Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G01R31/3177 ; G01R31/3181 ; G06F3/0484 ; G06F11/36 ; G06F11/22 ; G06F11/263 ; G06T11/20

Abstract:
A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.
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