Invention Grant
- Patent Title: Reducing power requirements and switching during logic built-in-self-test and scan test
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Application No.: US14851174Application Date: 2015-09-11
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Publication No.: US09651623B2Publication Date: 2017-05-16
- Inventor: Satya Rama S. Bhamidipati , Mary P. Kusko , Cedric Lichtenau
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Heslin Rothenberg Farley & Mesiti PC
- Agent Margaret McNamara; Matthew M. Hulihan
- Main IPC: G01R31/3185
- IPC: G01R31/3185 ; G01R31/317 ; G01R31/3177 ; G01R31/319

Abstract:
A number of switching transitions of flip-flops during testing is kept below a threshold. Scan-in test data is applied to the flip-flops. Testing result data scanned-out from the flip-flops is captured, and a prediction is made of a number of switching transitions of the flip-flops between a current capture clock cycle and a next capture clock cycle—in particular, for the next capture clock cycle—thereby using the scan-in test data for the next capture clock cycle and the testing result data scanned-out of the current capture clock cycle. Furthermore, the testing setup values are modified before the next testing cycle is executed based on the prediction in order to enter a new configuration of a testing circuit such that the predicted number of switching transitions of the flip-flops stays below the threshold. The testing setup values comprise parameters for modifying the capture clock cycle and a seed value for generating test patterns.
Public/Granted literature
- US20170074934A1 REDUCING POWER REQUIREMENTS AND SWITCHING DURING LOGIC BUILT-IN-SELF-TEST AND SCAN TEST Public/Granted day:2017-03-16
Information query
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