Invention Grant
- Patent Title: Bias circuit for stacked hall devices
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Application No.: US14533692Application Date: 2014-11-05
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Publication No.: US09651635B2Publication Date: 2017-05-16
- Inventor: Udo Ausserlechner
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Schiff Hardin LLP
- Main IPC: G01R33/07
- IPC: G01R33/07

Abstract:
Embodiments relate to stacks of Hall effect structures, in which the potential at the contacts of each Hall effect structure throughout a stack of Hall effect structures changes monotonically. An output associated with the Hall effect structure in each layer of the stack can be compared against the output of a counterpart Hall effect structure in another stack to ascertain the strength of an incident magnetic field.
Public/Granted literature
- US20160124055A1 BIAS CIRCUIT FOR STACKED HALL DEVICES Public/Granted day:2016-05-05
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