Disclosed is a memory controller, including: a host interface suitable for queuing a plurality of host commands from a host in a host command queue; a state register storing ready set bits respectively corresponding to the plurality of host commands; a memory command generating unit generating and queuing memory commands and state update information corresponding to the queued host commands in a memory command queue, respectively; and the memory command performing unit performing an operation in response to the queued memory commands. The memory command performing unit obtains state update information corresponding to the performed memory command from the memory command queue, and updates a ready set bit of a host command corresponding to the performed memory command based on the obtained state update information.