Invention Grant
- Patent Title: Computer processor employing dedicated hardware mechanism controlling the initialization and invalidation of cache lines
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Application No.: US14515231Application Date: 2014-10-15
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Publication No.: US09652230B2Publication Date: 2017-05-16
- Inventor: Roger Rawson Godard , Arthur David Kahlich , Norman Hardy , Allen Jay Baum
- Applicant: Mill Computing, Inc.
- Applicant Address: US CA Palo Alto
- Assignee: Mill Computing, Inc.
- Current Assignee: Mill Computing, Inc.
- Current Assignee Address: US CA Palo Alto
- Agency: Gordon & Jacobson, P.C.
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F12/0893 ; G06F12/0811 ; G06F12/0864 ; G06F12/02 ; G06F12/1027 ; G06F12/1009 ; G06F17/30 ; G06F12/0897
Abstract:
A computer processing system includes execution logic that generates memory requests that are supplied to a hierarchical memory system. The computer processing system includes a hardware map storing a number of entries associated with corresponding cache lines, where each given entry of the hardware map indicates whether a corresponding cache line i) currently stores valid data in the hierarchical memory system, or ii) does not currently store valid data in hierarchical memory system and should be interpreted as being implicitly zero throughout.
Public/Granted literature
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