Invention Grant
- Patent Title: Instruction and logic to control transfer in a partial binary translation system
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Application No.: US13996352Application Date: 2011-09-30
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Publication No.: US09652234B2Publication Date: 2017-05-16
- Inventor: Paul Caprioli , Martin G. Dixon , Brett L. Toll , Muawya M. Al-Otoom , Omar M. Shaikh
- Applicant: Paul Caprioli , Martin G. Dixon , Brett L. Toll , Muawya M. Al-Otoom , Omar M. Shaikh
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- International Application: PCT/US2011/054355 WO 20110930
- International Announcement: WO2013/048460 WO 20130404
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38

Abstract:
A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look-aside buffer (iTLB) to map original code pages and translated code pages. The method may comprise fetching an instruction from an original code page, determining whether the fetched instruction is a first instruction of a new code page and whether the original code page is deprecated. If both determinations return yes, the method may further comprise fetching a next instruction from a translated code page. If either determinations returns no, the method may further comprise decoding the instruction and fetching the next instruction from the original code page.
Public/Granted literature
- US20130305019A1 Instruction and Logic to Control Transfer in a Partial Binary Translation System Public/Granted day:2013-11-14
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