Invention Grant
- Patent Title: Predicting out-of-order instruction level parallelism of threads in a multi-threaded processor
-
Application No.: US13172218Application Date: 2011-06-29
-
Publication No.: US09652243B2Publication Date: 2017-05-16
- Inventor: Ioana Monica Burcea , Alper Buyuktosunoglu , Brian Robert Prasky , Vijayalakshmi Srinivasan
- Applicant: Ioana Monica Burcea , Alper Buyuktosunoglu , Brian Robert Prasky , Vijayalakshmi Srinivasan
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ference & Associates LLC
- Main IPC: G06F9/38
- IPC: G06F9/38

Abstract:
Systems and methods for predicting out-of-order instruction-level parallelism (ILP) of threads being executed in a multi-threaded processor and prioritizing scheduling thereof are described herein. One aspect provides for tracking completion of instructions using a global completion table having a head segment and a tail segment; storing prediction values for each instruction in a prediction table indexed via instruction identifiers associated with each instruction, a prediction value being configured to indicate an instruction is predicted to issue from one of: the head segment and the tail segment; and predicting threads with more instructions issuing from the tail segment have a higher degree of out-of-order instruction-level parallelism. Other embodiments and aspects are also described herein.
Public/Granted literature
- US20130007423A1 PREDICTING OUT-OF-ORDER INSTRUCTION LEVEL PARALLELISM OF THREADS IN A MULTI-THREADED PROCESSOR Public/Granted day:2013-01-03
Information query