Invention Grant
- Patent Title: Method for integrating non-volatile memory cells with static random access memory cells and logic transistors
-
Application No.: US14656832Application Date: 2015-03-13
-
Publication No.: US09653164B2Publication Date: 2017-05-16
- Inventor: Cheong Min Hong , Laureen H. Parker
- Applicant: FREESCALE SEMICONDUCTOR, INC.
- Applicant Address: US TX Austin
- Assignee: NXP USA, INC.
- Current Assignee: NXP USA, INC.
- Current Assignee Address: US TX Austin
- Main IPC: G11C14/00
- IPC: G11C14/00 ; H01L29/51 ; H01L21/265 ; H01L21/28 ; H01L29/423 ; H01L27/11524 ; H01L27/11534

Abstract:
A method of making a semiconductor device is described. The method comprises depositing a first polysilicon layer in a non-volatile memory (NVM) region and a logic region of a substrate. A first coating layer is deposited over the first polysilicon layer. The first coating layer and the first polysilicon layer are patterned to form a first gate in the NVM region. A memory cell is formed including the first gate. The first coating layer and the first layer of polysilicon in the logic region are removed and a logic gate polysilicon layer is deposited. The logic gate polysilicon layer is patterned to form a second gate in the logic region while the logic gate polysilicon layer is removed from the NVM region. Source/drain regions of the memory cell and the second gate are implanted concurrently.
Public/Granted literature
Information query