Invention Grant
- Patent Title: Semiconductor device and method of fabricating 3D package with short cycle time and high yield
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Application No.: US14887561Application Date: 2015-10-20
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Publication No.: US09653445B2Publication Date: 2017-05-16
- Inventor: Yaojian Lin
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/66 ; H01L21/768 ; H01L21/78 ; H01L25/00 ; H01L25/16 ; H01L21/48 ; H01L23/538 ; H01L23/498 ; H01L23/31 ; H01L21/56

Abstract:
A method of making a semiconductor device comprises the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while simultaneously forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU, and disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD. A resolution of the second manufacturing line is greater than a resolution of the first manufacturing line.
Public/Granted literature
- US20160118332A1 Semiconductor Device and Method of Fabricating 3D Package With Short Cycle Time and High Yield Public/Granted day:2016-04-28
Information query
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