Invention Grant
- Patent Title: Digital filter and timing signal generation circuit
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Application No.: US14634354Application Date: 2015-02-27
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Publication No.: US09658630B2Publication Date: 2017-05-23
- Inventor: Tetsutaro Hashimoto
- Applicant: FUJITSU LIMITED
- Applicant Address: JP Kawasaki
- Assignee: FUJITSU LIMITED
- Current Assignee: FUJITSU LIMITED
- Current Assignee Address: JP Kawasaki
- Agency: Arent Fox LLP
- Priority: JP2014-057034 20140319
- Main IPC: H04B1/10
- IPC: H04B1/10 ; G05F1/46

Abstract:
A digital filter includes: a minimum-value holder that holds a minimum value of a measurement value inputted in the minimum-value holder and that outputs the minimum value as a held value; a limit-value circuit that receives the held value and that outputs the held value as a limit value in a case where the held value remains minimum during predetermined cycles; and an output controller that receives a maximum value, the measurement value, and the limit value, the maximum value defining an upper limit, outputs the measurement value as an output value if the measurement value is smaller than the limit value, and outputs the maximum value as the output value if the measurement value is equal to or larger than the limit value.
Public/Granted literature
- US20150268679A1 DIGITAL FILTER AND TIMING SIGNAL GENERATION CIRCUIT Public/Granted day:2015-09-24
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