Techniques are disclosed relating to a system that implements direct memory access (DMA). In one embodiment, an apparatus is disclosed that includes a dedicated data transfer management (DTM) circuit. The DTM circuit is configured to provide commands to a direct memory access (DMA) controller coupled to a bus to facilitate the DMA controller retrieving portions of a data object to be transmitted to a peripheral circuit via the bus. In some embodiments, the DTM is configured to assemble a data packet having a payload supplied by a processor, where the DTM circuit is configured to assemble the data packet by generating direct memory access (DMA) requests for the DMA controller. In such an embodiment, the DMA requests cause a plurality of peripheral circuits coupled to the bus to transfer portions of the data packet over the bus.