Invention Grant
- Patent Title: Mid command buffer preemption for graphics workloads
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Application No.: US13931915Application Date: 2013-06-29
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Publication No.: US09659342B2Publication Date: 2017-05-23
- Inventor: Hema Chand Nalluri , Aditya Navale , Murali Ramadoss , Jeffery S. Boles
- Applicant: Hema Chand Nalluri , Aditya Navale , Murali Ramadoss , Jeffery S. Boles
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F9/48
- IPC: G06F9/48 ; G06T1/60 ; G06T1/20

Abstract:
Mid-command buffer preemption is described for graphics workloads in a graphics processing environment. In one example, instructions of a first context are executed at a graphics processor, the first context has a sequence of instructions in an addressable buffer and at least one of the instructions is a preemption instruction. Upon executing the preemption instruction, execution of the first context is stopped before the sequence of instructions is completed. An address is stored for an instruction with which the first context will be resumed. The second context is executed, and upon completion of the execution of the second context, the execution of the first context is resumed at the stored address.
Public/Granted literature
- US20150002522A1 MID COMMAND BUFFER PREEMPTION FOR GRAPHICS WORKLOADS Public/Granted day:2015-01-01
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