A memory includes first signal-lines, second signal-lines and resistance-change memory cells. First and second drivers can supply power to the first and second signal-lines, respectively. The second driver increases a voltage of a selected second signal-line in a write-loop higher than that in a previous write-loop. The write-loop includes a write operation and a verify operation. A voltage increase width of the selected second signal-line at a time of transition from a first write-loop to a second write-loop is larger than a voltage increase width of the selected second signal-line at a time of transition from the second write-loop to a third write-loop. A voltage increase width of the selected second signal-line at a time of transition from the second write-loop to the third write-loop is smaller than a voltage increase width of the selected second signal-line at a time of transition from the third write-loop to a forth write-loop.