Invention Grant
- Patent Title: Asymmetric source/drain depths
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Application No.: US15369635Application Date: 2016-12-05
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Publication No.: US09659826B2Publication Date: 2017-05-23
- Inventor: Cheng-Yi Peng , Yu-Lin Yang , Chia-Cheng Ho , Jung-Piao Chiu , Tsung-Lin Lee , Chih Chieh Yeh , Chih-Sheng Chang , Yee-Chia Yeo
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/8238 ; H01L29/08 ; H01L29/10 ; H01L29/161 ; H01L29/20 ; H01L27/092

Abstract:
A method for fabricating a semiconductor device includes forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region. The method further includes forming a tensile strained semiconductor layer on the relaxed semiconductor layer, etching a portion of the tensile strained semiconductor layer in the p-type region, forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region, forming a first gate in the n-type region and a second gate in the p-type region, and forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate. The second set of source/drain features are deeper than the first set of source/drain features.
Public/Granted literature
- US20170084498A1 ASYMMETRIC SOURCE/DRAIN DEPTHS Public/Granted day:2017-03-23
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