Invention Grant
- Patent Title: Interconnect structures for wafer level package and methods of forming same
-
Application No.: US15052105Application Date: 2016-02-24
-
Publication No.: US09659896B2Publication Date: 2017-05-23
- Inventor: Chih-Hao Chang , Tsung-Hsien Chiang , Guan-Yu Chen , Wei Sen Chang , Tin-Hao Kuo , Hao-Yi Tsai , Chen-Hua Yu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L21/48 ; H01L21/56
Abstract:
A method for forming a device package includes forming a molding compound around a plurality of dies and laminating a polymer layer over the dies. A top surface of the dies is covered by a film layer while the molding compound is formed, and the polymer layer extends laterally past edge portions of the dies. The method further includes forming a conductive via in the polymer layer, wherein the conductive via is electrically connected to a contact pad at a top surface of one of the dies.
Public/Granted literature
- US20160172329A1 Interconnect Structures for Wafer Level Package and Methods of Forming Same Public/Granted day:2016-06-16
Information query
IPC分类:
