Invention Grant
- Patent Title: High-voltage field-effect transistor having multiple implanted layers
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Application No.: US13941119Application Date: 2013-07-12
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Publication No.: US09660053B2Publication Date: 2017-05-23
- Inventor: Vijay Parthasarathy , Sujit Banerjee
- Applicant: Power Integrations, Inc.
- Applicant Address: US CA San Jose
- Assignee: Power Integrations, Inc.
- Current Assignee: Power Integrations, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Blakely Sokoloff Taylor & Zafman LLP
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/10 ; H01L29/66 ; H01L29/78 ; H01L21/265 ; H01L29/40 ; H01L29/423

Abstract:
A method for fabricating a high-voltage field-effect transistor includes forming a body region, a source region, and a drain region in a semiconductor substrate. The drain region is separated from the source region by the body region. Forming the drain region includes forming an oxide layer on a surface of the semiconductor substrate over the drain region and performing a plurality of ion implantation operations through the oxide layer while tilting the semiconductor substrate such that ion beams impinge on the oxide layer at an angle that is offset from perpendicular. The plurality of ion implantation operations form a corresponding plurality of separate implanted layers within the drain region. Each of the implanted layers is formed at a different depth within the drain region.
Public/Granted literature
- US20150014770A1 HIGH-VOLTAGE FIELD-EFFECT TRANSISTOR HAVING MULTIPLE IMPLANTED LAYERS Public/Granted day:2015-01-15
Information query
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