Invention Grant
- Patent Title: Impedance matching for an integrated circuit of a magnetic disk device
-
Application No.: US15059146Application Date: 2016-03-02
-
Publication No.: US09666226B1Publication Date: 2017-05-30
- Inventor: Nobuyoshi Yamasaki
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Patterson & Sheridan, LLP
- Main IPC: G11B5/02
- IPC: G11B5/02 ; G11B20/10 ; G11B5/09

Abstract:
An integrated circuit connectable to a signal transmission path of a storage device includes an impedance setting circuit including a plurality of switches, a detector configured to detect an input signal level, and a decoder. The decoder controls one or more switches of the impedance setting circuit based on the detected input signal level so as to match an impedance of the integrated circuit with an impedance of the signal transmission path.
Public/Granted literature
- US20170148481A1 IMPEDANCE MATCHING FOR AN INTEGRATED CIRCUIT OF A MAGNETIC DISK DEVICE Public/Granted day:2017-05-25
Information query
IPC分类: