Invention Grant
- Patent Title: Access methods and circuits for memory devices having multiple banks
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Application No.: US14258950Application Date: 2014-04-22
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Publication No.: US09666255B2Publication Date: 2017-05-30
- Inventor: Thinh Tran , Joseph Tzou , Jun Li
- Applicant: Cypress Semiconductor Corporation
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G11C8/12
- IPC: G11C8/12 ; G11C8/18 ; G11C11/418 ; G11C11/419 ; G11C7/10 ; G11C11/413

Abstract:
A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different banks and preventing access to any one of the plurality of banks by more than one address of the one cycle; wherein each bank includes memory cells arranged into rows and columns that comprise the storage locations.
Public/Granted literature
- US20140340978A1 ACCESS METHODS AND CIRCUITS FOR MEMORY DEVICES HAVING MULTIPLE BANKS Public/Granted day:2014-11-20
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