Invention Grant
- Patent Title: Package substrate differential impedance optimization for 25 GBPS and beyond
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Application No.: US14729050Application Date: 2015-06-02
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Publication No.: US09666544B2Publication Date: 2017-05-30
- Inventor: Longqiang Zu , Li-Chang Hsiao
- Applicant: Sarcina Technology LLC
- Applicant Address: US CA Palo Alto
- Assignee: SARCINA TECHNOLOGY LLC
- Current Assignee: SARCINA TECHNOLOGY LLC
- Current Assignee Address: US CA Palo Alto
- Agency: Chen Yoshimura LLP
- Main IPC: H01L23/66
- IPC: H01L23/66 ; G06F17/50 ; H01L23/498 ; H01L23/538
Abstract:
A package design method is disclosed for the optimization of package differential impedance at data rates of 25 Gb/s and beyond. The method optimizes the differential impedance of package vertical interconnections of BGA ball, via, and PTH as well as around the joint between the vertical interconnection and the horizontal interconnection of trace. At 8 ps rise time, a
Public/Granted literature
- US20160358866A1 PACKAGE SUBSTRATE DIFFERENTIAL IMPEDANCE OPTIMIZATION FOR 25 GBPS AND BEYOND Public/Granted day:2016-12-08
Information query
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