- Patent Title: Transistor with a low-k sidewall spacer and method of making same
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Application No.: US15227182Application Date: 2016-08-03
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Publication No.: US09666679B2Publication Date: 2017-05-30
- Inventor: Clement Gaumer , Daniel Benoit
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Gardere Wynne Sewell LLP
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/417 ; H01L29/78 ; H01L21/285 ; H01L21/84 ; H01L29/06 ; H01L29/423 ; H01L29/45 ; H01L29/49 ; H01L29/66

Abstract:
A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.
Public/Granted literature
- US20160343814A1 TRANSISTOR WITH A LOW-K SIDEWALL SPACER AND METHOD OF MAKING SAME Public/Granted day:2016-11-24
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