Invention Grant
- Patent Title: High performance integrated tunable impedance matching network with coupled merged inductors
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Application No.: US14690212Application Date: 2015-04-17
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Publication No.: US09667217B2Publication Date: 2017-05-30
- Inventor: Chih-Chieh Cheng , Tero Tapio Ranta , Richard Bryon Whatley , Vikram Sekar
- Applicant: Peregrine Semiconductor Corporation
- Applicant Address: US CA San Diego
- Assignee: Peregrine Semiconductor Corporation
- Current Assignee: Peregrine Semiconductor Corporation
- Current Assignee Address: US CA San Diego
- Agency: Jaquez Land Greenhaus LLP
- Agent Martin J. Jaquez, Esq.; John Land, Esq.
- Main IPC: H03H7/38
- IPC: H03H7/38 ; H03H3/00 ; H01F17/00
Abstract:
A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors.
Public/Granted literature
- US20160308506A1 High Performance Integrated Tunable Impedance Matching Network with Coupled Merged Inductors Public/Granted day:2016-10-20
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