- Patent Title: Methods and devices for preventing overhangs in a finishing layer of metal formed on electrical contact surfaces when fabricating multi-layer printed circuit boards
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Application No.: US15139122Application Date: 2016-04-26
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Publication No.: US09668340B1Publication Date: 2017-05-30
- Inventor: Jack Ajoian , Lea-Teng Lee
- Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H05K1/00
- IPC: H05K1/00 ; H05K1/02 ; H05K3/46 ; H05K3/18 ; H05K3/00 ; H05K1/09 ; H05K3/06 ; H05K1/11

Abstract:
A build-up process for fabricating a multi-layer PCB is provided that prevents, or at least reduces the lengths of, overhangs in the finishing metal layer that is plated onto the electrical contact metal layer. The metal seed layer is etched away prior to plating the finishing metal layer onto the electrical contact metal layer. The electrical contact metal layer is covered with a layer of dielectric material, which is then patterned to selectively expose preselected areas of the electrical contact metal layer. The exposed preselected areas of the electrical contact metal layer are then plated with the finishing layer of metal. The result is that overhangs are eliminated or at least greatly reduced in length. In addition, the dielectric material layer serves a function similar to that of a solder mask and obviates the need to apply the oxide to serve as a solder mask.
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