Invention Grant
- Patent Title: Apparatus and method for a voltage regulator with improved power supply reduction ratio (PSRR) with reduced parasitic capacitance on bias signal lines
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Application No.: US14073106Application Date: 2013-11-06
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Publication No.: US09671801B2Publication Date: 2017-06-06
- Inventor: Ambreesh Bhattad , Ludmil Nikolov
- Applicant: Dialog Semiconductor GmbH
- Applicant Address: DE Kirchhiem/Teck-Nabern
- Assignee: Dialog Semiconductor GmbH
- Current Assignee: Dialog Semiconductor GmbH
- Current Assignee Address: DE Kirchhiem/Teck-Nabern
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman
- Main IPC: G05F1/563
- IPC: G05F1/563 ; G05F1/575

Abstract:
An apparatus and method for a system with improved power supply rejection ratio (PSRR) over a wide frequency range. The improved PSRR is achieved by negating the influence of the parasitic capacitance associated with the bias lines and the introduction of a regulated power supply with embodiments associated with providing a ripple free and regulated supply. With reduction of parasitic capacitance, and providing an ENABLE switch by a pre-regulated supply, the degradation of the PSRR is achieved. The embodiments include both n-channel and p-channel MOSFETs implementations, and a positive and negative regulated power supply voltage. With the combined influence of the utilization of the VREG supply, and the lowering of battery-to-bias line capacitance using design layout and improved floor planning an improved PSRR over a wide frequency distribution is achieved.
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