A hardware device controller includes a controlling unit, a relay unit, and a watchdog timer. The controlling unit outputs a control signal to control a hardware device. The relay unit outputs, on the basis of the control signal, a control signal to the hardware device. When not receiving a first signal output from the controlling unit via the relay unit for a predetermined length of time or longer, the watchdog timer outputs a second signal. When the second signal is output, the controlling unit and the relay unit perform initialization process, and the hardware device stops driving.