Fault detection for an interconnect bus includes performing safety register validation including validating correct operation of a safety register in a slave circuit. The safety register is reserved for validation operations. Write bus validation is performed where, over an address range of the slave circuit, received write addresses within the address range are stored in the safety register of the slave circuit and read back by a master circuit for validation. Read bus validation is performed where, over the address range of the slave circuit, received read addresses within the address range are provided back to the master circuit for validation.