A system comprises a first cache controller and at least a second cache controller. The first cache controller and the second cache controller each include a cache memory interface, an inter-cache controller communication link configured for bidirectional communication with the other cache controller, a first peripheral interface, a second peripheral interface, and logic circuitry. The first peripheral interface communicates with a first host device and the second peripheral interface communicates with a second host device. The first host device and the second host device are each connected to the first and second cache controllers by the first and second peripheral interfaces. The logic circuitry loads a cache command from a cache command memory of the first host device, loads a cache command from a cache command memory of the second cache controller, and performs the cache commands.