Invention Grant
- Patent Title: Isolated through silicon via and isolated deep silicon via having total or partial isolation
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Application No.: US13874656Application Date: 2013-05-01
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Publication No.: US09673081B2Publication Date: 2017-06-06
- Inventor: Hadi Jebory , David J. Howard , Marco Racanelli , Edward Preisler
- Applicant: Newport Fab, LLC
- Applicant Address: US CA Newport Beach
- Assignee: Newport Fab, LLC
- Current Assignee: Newport Fab, LLC
- Current Assignee Address: US CA Newport Beach
- Agency: Farjami & Farjami LLP
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/761 ; H01L29/06 ; H01L21/768 ; H01L23/48 ; H01L21/225 ; H01L21/265

Abstract:
Disclosed are a structure for improving electrical signal isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench having sidewalls disposed in the semiconductor substrate. An isolation region may be formed along at least an upper portion of the sidewalls of the deep trench, and a metallic filler may be disposed in the deep trench. The isolation region may include a PN junction formed by one or more of ion implantation and annealing, deposition of highly doped polysilicon and out diffusion, and gas phase doping and annealing. In the alternative, the isolation region may be a dielectric isolation region formed by one or more of uniform dielectric deposition, partial dieletric deposition, and dielectric deposition by ionic reaction.
Public/Granted literature
- US20130313682A1 Isolated Through Silicon Via and Isolated Deep Silicon Via Having Total or Partial Isolation Public/Granted day:2013-11-28
Information query
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