Invention Grant
- Patent Title: Method of manufacturing stacked semiconductor package
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Application No.: US14661155Application Date: 2015-03-18
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Publication No.: US09673185B2Publication Date: 2017-06-06
- Inventor: Young-ho Joung , Jong-gyu Kim
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-Si, Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-Si, Gyeonggi-Do
- Agency: Lee & Morse P.C.
- Priority: KR10-2014-0050926 20140428
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/48 ; H01L23/538 ; H01L21/50 ; H01L23/544 ; H01L25/00 ; H01L21/268 ; H01L21/768 ; H01L21/48 ; H01L21/67 ; H01L23/00 ; H01L25/10 ; H01L23/31
Abstract:
A method of manufacturing a stacked semiconductor package includes forming a semiconductor package, the semiconductor package having one or more semiconductor chips on an upper surface of a printed circuit board (PCB), and a mold layer covering the upper surface of the PCB, marking the semiconductor package with an identification mark by scanning a laser of a laser supply apparatus onto the semiconductor package, controlling a focus level of the laser, and performing laser drilling on the mold layer of the semiconductor package to form openings.
Public/Granted literature
- US20150311187A1 METHOD OF MANUFACTURING STACKED SEMICONDUCTOR PACKAGE Public/Granted day:2015-10-29
Information query
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