Invention Grant
- Patent Title: Integrated electrostatic discharge (ESD) clamping for an LDMOS transistor device having a bipolar transistor
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Application No.: US14966688Application Date: 2015-12-11
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Publication No.: US09673188B2Publication Date: 2017-06-06
- Inventor: Weize Chen , Patrice M. Parris
- Applicant: Weize Chen , Patrice M. Parris
- Applicant Address: US TX Austin
- Assignee: NXP USA, INC.
- Current Assignee: NXP USA, INC.
- Current Assignee Address: US TX Austin
- Main IPC: H01L27/07
- IPC: H01L27/07 ; H01L27/02 ; H01L21/762 ; H01L29/78 ; H01L29/66 ; H01L21/768 ; H01L29/06 ; H01L29/10

Abstract:
A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body region.
Public/Granted literature
- US20160099240A1 INTEGRATED ELECTROSTATIC DISCHARGE (ESD) CLAMPING Public/Granted day:2016-04-07
Information query
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