Chip structures that include distributed wiring layouts and fabrication methods for forming such chip structures. A device structure is formed that includes a plurality of first device regions and a plurality of second device regions. A first wiring level is formed that includes a first wire coupled with the first device regions. A second wiring level is formed that includes a second wire coupled with the second device regions. The first wiring level is vertically separated from the second wiring level by a buried oxide layer of the silicon-on-insulator substrate.