A display panel is provided, which includes a substrate and a first metal layer on the substrate. The first metal layer includes a gate electrode and a gate line connecting to the gate electrode. A first insulation layer is disposed on the first metal layer. A planarization layer is disposed on the first insulation layer. An opening, overlapping the gate electrode, is defined by sidewalls of the planarization layer and a surface of the first insulation layer. An active layer is disposed on the opening and the planarization layer. A second metal layer is disposed on the semiconductor layer, and includes a source electrode contacting the active layer and a data line connecting to the source electrode. The planarization layer and the first insulation layer are disposed between the data line and the gate line.