- Patent Title: Vertical junctionless transistor device and manufacturing methods
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Application No.: US14830731Application Date: 2015-08-19
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Publication No.: US09673322B2Publication Date: 2017-06-06
- Inventor: Deyuan Xiao
- Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Applicant Address: CN Shanghai CN Beijing
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee Address: CN Shanghai CN Beijing
- Agency: Kilpatrick Townsend and Stockton LLP
- Priority: CN201410421827 20140826
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/66 ; H01L29/78 ; H01L29/20 ; H01L29/08 ; H01L29/10 ; H01L29/06 ; H01L21/02 ; H01L21/306

Abstract:
A method for forming a semiconductor device includes forming a fin device structure in a buffer layer on a substrate. The fin device structure includes a lower portion extending over the silicon substrate and a fin structure protruding above the lower portion. The method also includes forming a sacrificial layer disposed over the fin device structure and forming a device semiconductor layer disposed over a surface of the sacrificial layer. A gate dielectric layer is then formed and is disposed over a surface of the device semiconductor layer. A gate electrode layer is formed and disposed over a surface of the gate dielectric layer. The method includes removing a portion of the sacrificial layer to form a cavity surrounding the fin structure and performing an oxidation process to form a thermal oxide layer in the cavity surrounding the side surface of the fin structure.
Public/Granted literature
- US20160064557A1 VERTICAL JUNCTIONLESS TRANSISTOR DEVICE AND MANUFACTURING METHODS Public/Granted day:2016-03-03
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