Invention Grant
- Patent Title: Duty cycle calibration circuit
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Application No.: US15082188Application Date: 2016-03-28
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Publication No.: US09673789B1Publication Date: 2017-06-06
- Inventor: Jade Deng
- Applicant: VIA Alliance Semiconductor Co., Ltd.
- Applicant Address: CN Shanghai
- Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee Address: CN Shanghai
- Agency: McClure, Qualey & Rodack, LLP
- Priority: CN201510885622 20151204
- Main IPC: H03K3/017
- IPC: H03K3/017 ; H03K19/20

Abstract:
A signal-generating circuit includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first inverter, a second inverter, and a third inverter. The first P-type transistor supplies a supply voltage to a first node according to an input signal. Both of the second P-type transistor and the first N-type transistor couple the first node to a second node according to the input signal. The second N-type transistor couples the first node to a ground according to the input signal. The first inverter is coupled to the second node to generate a first signal. The second inverter is coupled between the first node and a third node. The third inverter is coupled to the third node to generate a second signal. The second signal and the first signal are the reverse of each other and synchronous.
Public/Granted literature
- US20170163247A1 DUTY CYCLE CALIBRATION CIRCUIT Public/Granted day:2017-06-08
Information query
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