Invention Grant
- Patent Title: Circuit arrangement with interference protection
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Application No.: US12778109Application Date: 2010-05-11
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Publication No.: US09673913B2Publication Date: 2017-06-06
- Inventor: Pietro Brenner , Edmund Götz
- Applicant: Pietro Brenner , Edmund Götz
- Applicant Address: DE Neubiberg
- Assignee: Intel Deutschland GmbH
- Current Assignee: Intel Deutschland GmbH
- Current Assignee Address: DE Neubiberg
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H03K5/00
- IPC: H03K5/00 ; H04B15/00

Abstract:
A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device coupled to at least the supply line to suppress any interfering signals from being applied to the supply line.
Public/Granted literature
- US20100219882A1 CIRCUIT ARRANGEMENT WITH INTERFERENCE PROTECTION Public/Granted day:2010-09-02
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