Invention Grant
- Patent Title: Two-step interconnect testing of semiconductor dies
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Application No.: US14247019Application Date: 2014-04-07
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Publication No.: US09678142B2Publication Date: 2017-06-13
- Inventor: Julien Ryckaert , Erik Jan Marinissen , Dimitri Linten
- Applicant: IMEC
- Applicant Address: BE Leuven
- Assignee: IMEC
- Current Assignee: IMEC
- Current Assignee Address: BE Leuven
- Agency: Knobbe, Martens, Olson & Bear LLP
- Priority: EP13162824 20130408
- Main IPC: G01R31/20
- IPC: G01R31/20 ; G01R31/26 ; H01L21/66 ; G01R31/3185 ; H01L25/065

Abstract:
The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.
Public/Granted literature
- US20140300379A1 TWO-STEP INTERCONNECT TESTING OF SEMICONDUCTOR DIES Public/Granted day:2014-10-09
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