The invention relates to a system and method for improved power sequencing within an embedded flash memory device for a plurality of voltage sources. In one embodiment, a power sequence enabling circuit comprises a PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first voltage source. During a power up time period, a voltage output from the first voltage source ramps upward, toward a voltage output from a second voltage source through the PMOS transistor. During a power down period, a voltage from the second voltage source ramps downward toward an intermediate voltage greater than zero volts through the first NMOS transistor.