- Patent Title: Instruction sequence buffer to enhance branch prediction efficiency
-
Application No.: US13879365Application Date: 2011-10-12
-
Publication No.: US09678755B2Publication Date: 2017-06-13
- Inventor: Mohammad Abdallah
- Applicant: Mohammad Abdallah
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott, LLP
- International Application: PCT/US2011/055917 WO 20111012
- International Announcement: WO2012/051262 WO 20120419
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38

Abstract:
A method for outputting alternative instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor. A frequently miss-predicted branch instruction is identified, wherein the predicted outcome of the branch instruction is frequently wrong. An alternative instruction sequence for the branch instruction target is stored into a buffer. On a subsequent hit to the branch instruction where the predicted outcome of the branch instruction was wrong, the alternative instruction sequence is output from the buffer.
Public/Granted literature
- US20130311759A1 INSTRUCTION SEQUENCE BUFFER TO ENHANCE BRANCH PREDICTION EFFICIENCY Public/Granted day:2013-11-21
Information query