A trace of a bounded liveness failure of a system component is received, by one or more processors, along with fairness constraints and liveness assertion conditions. One or more processors generate randomized values for unassigned input values and register values, of the trace, and simulate traversal of each of a sequence of states of the trace. One or more processors determine whether traversing the sequence of states of the trace results in a repetition of a state, and responsive to determining that traversing the sequence of states of the trace does result in a repetition of a state, and the set of fairness constraints are asserted within the repetition of a state, and that the continuous liveness assertion conditions are maintained throughout the repetition of the state, a concrete counterexample of a liveness property of the system component is reported.