Invention Grant
- Patent Title: Disabling cache portions during low voltage operations
-
Application No.: US13652480Application Date: 2012-10-16
-
Publication No.: US09678878B2Publication Date: 2017-06-13
- Inventor: Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
- Applicant: Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Mnemoglyphics, LLC
- Agent Lawrence M. Mennemeier
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/126 ; G06F12/0864 ; G06F12/0804 ; G06F1/32
Abstract:
Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
Public/Granted literature
- US20140108733A1 DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS Public/Granted day:2014-04-17
Information query
