Invention Grant
- Patent Title: Stacked clock-generation circuit
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Application No.: US15245294Application Date: 2016-08-24
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Publication No.: US09679623B2Publication Date: 2017-06-13
- Inventor: Rahul Todi , Mark Stefan Oude Alink
- Applicant: Dialog Semiconductor B.V.
- Applicant Address: NL 's-Hertogenbosch
- Assignee: Dialog Semiconductor B.V.
- Current Assignee: Dialog Semiconductor B.V.
- Current Assignee Address: NL 's-Hertogenbosch
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman
- Priority: DE102015216637 20150831
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C5/02 ; G11C5/06 ; G11C7/10

Abstract:
An electronic circuit is disclosed for dividing the frequency of a periodic signal, wherein at least one of the memory elements is arranged with its output terminal connected to the input terminal of another memory element wherein the electronic circuit is configured to generate an output signal having a smaller fundamental frequency than the clock signal at at least one of the output terminals. Each memory element is configured to change and hold a voltage at the output terminal based on a voltage at the input terminal at times controlled by a clock signal received at the clock terminal. At least two of the memory elements are stacked in the sense that the bottom terminal of a first memory element is connected to the top terminal of a second memory element to enable the charge to flow from the first memory element to the second memory element.
Public/Granted literature
- US20170062027A1 Stacked Clock-Generation Circuit Public/Granted day:2017-03-02
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