A memory device includes a semiconductor pillar, a first memory cell that includes a first memory film between a first word line and a side surface of the semiconductor pillar, a second memory cell that includes a second memory film between a second word line and the side surface of the semiconductor pillar, and a control circuit configured to carry out first and second operations on the first memory cell and the second memory cell during a reading operation. During the first operation, a read voltage is applied to the first word line and a read pass voltage is applied to the second word line, and during the second operation following the first operation, a first voltage is applied to the second word line, such that a potential of the second word line is lower than a potential of the semiconductor pillar.