Invention Grant
- Patent Title: Masking for high temperature implants
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Application No.: US14807377Application Date: 2015-07-23
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Publication No.: US09679776B2Publication Date: 2017-06-13
- Inventor: Andrew M. Waite , Naushad Variam
- Applicant: Varian Semiconductor Equipment Associates, Inc.
- Applicant Address: US MA Gloucester
- Assignee: Varian Semiconductor Equipment Associates, Inc.
- Current Assignee: Varian Semiconductor Equipment Associates, Inc.
- Current Assignee Address: US MA Gloucester
- Agency: Nields, Lemack & Frame, LLC
- Main IPC: H01L21/425
- IPC: H01L21/425 ; H01L21/266 ; H01L21/02 ; H01L21/308 ; H01L21/311
Abstract:
A method for the selective implantation of a workpiece is disclosed. In place of conventional photoresist, a two layer structure is used. The first layer, referred to as the protective layer, is applied directly to the workpiece and protects the workpiece from harmful etching processes. Additionally, the protective layer has limited ability to stop ions from impacting the workpiece. The second layer, referred to as the blocking layer, which is formed on a portion of the protective layer, is used to block ions from impacting the underlying workpiece. Advantageously, the blocking layer may be selectively etched without affecting the protective layer. Additionally, the protective layer can be removed without affecting the underlying workpiece. Through the use of this two layer technique, high temperature selective implants may be performed on a variety of different semiconductor devices.
Public/Granted literature
- US20170025277A1 Masking For High Temperature Implants Public/Granted day:2017-01-26
Information query
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