Invention Grant
- Patent Title: Planarization method, method for manufacturing semiconductor structure, and semiconductor structure
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Application No.: US14990526Application Date: 2016-01-07
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Publication No.: US09679782B1Publication Date: 2017-06-13
- Inventor: Yu-Ting Yen , Ying-Ho Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L21/3115
- IPC: H01L21/3115 ; H01L21/3215 ; H01L21/02 ; H01L21/321 ; H01L21/3205 ; H01L21/3105
Abstract:
A planarization method includes at least two steps. One of the steps is to implant at least one impurity into a wafer to form a polish stop layer in the wafer. The other one of the steps is to polish a top surface of the wafer until reaching the polish stop layer.
Information query
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