Invention Grant
- Patent Title: Multi-patterning to form vias with straight profiles
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Application No.: US15223572Application Date: 2016-07-29
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Publication No.: US09679804B1Publication Date: 2017-06-13
- Inventor: Chun-Kai Chen , Jung-Hau Shiu , Chia Cheng Chou , Chung-Chi Ko , Tze-Liang Lee , Chih-Hao Chen , Shing-Chyang Pan
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/768 ; H01L21/02 ; H01L21/311

Abstract:
A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.
Information query
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